Signed integer arithmetic

[bob]

When you deal with signed integers the sign bit twists the whole addition process in hardware. I ran into this during some assembly experiments last year. You might add two positives fine but negatives create carry issues that trip flags unexpectedly. The processor uses two's complement to make subtraction just another add operation. But you have to watch for overflow when the result exceeds the bit width. I always check the overflow flag after operations like that.
You get the idea once you flip bits and add one for negatives yourself. I tried it on paper first and it clicked fast. Your code runs smoother when you grasp how the ALU handles the sign extension during shifts. Perhaps the hardware designer chose two's complement because it avoids separate circuits for subtraction. Now you see why arithmetic right shifts preserve the sign bit unlike logical ones. I messed up a few shifts early on until I tested with actual values. Or consider a 32 bit word where the high bit decides positive or negative. You add numbers and the carry propagates from low bits upward. But partial results can fool you if you ignore the sign. I noticed that in some debug sessions with registers.
Also the range stays asymmetric with one extra negative value possible. You lose symmetry because zero takes a spot in positives. I explored that asymmetry in some performance tweaks for loops. Then multiplication of signed values needs careful handling of the high bits to avoid wrong signs. Perhaps you extend signs before multiplying to keep accuracy. I prefer testing edge cases like max negative times one. But the processor might set flags differently based on the mode. You learn to read those flags to catch errors quick. Now imagine mixing signed and unsigned in the same register bank and chaos follows. I avoid that mix after one bad porting job.
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