10-05-2022, 01:09 AM
But then you wonder about the register count needed to hold everything useful. I push for bigger banks in modern chips so programs avoid spilling over to slower spots. Or perhaps the instruction bits grow longer to name those extra registers clearly. You gain performance edges in loops that repeat math steps often. Also the design favors simpler decode steps since no address calculations mix in. Maybe that explains why certain architectures stick to this pattern for their core ops.
You watch how load store flows rely on separate moves to fetch values first. I find that separation helps scheduling in out of order execution engines. But it demands careful coding to preload registers ahead of use. Or the compiler works harder to reuse values stored locally. You see reduced bus traffic overall which eases power draw in tight systems. And fragments of code run smoother without constant memory waits interrupting the flow. Perhaps this pattern scales better when clock speeds climb higher each generation.
I notice tradeoffs appear when programs need lots of variables at once. You might hit limits forcing extra stores and loads anyway in complex routines. But the base speed from register ops still wins in benchmarks for numeric work. Or think about vector extensions that pack multiple register actions together. You benefit from parallelism without extra memory hops slowing progress. Also the whole execution unit stays busier because operands arrive instantly from nearby spots.
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