05-21-2019, 08:41 PM
I recall telling you about the control store holding tiny steps. Each microinstruction fires signals to the datapath. You load the address from the instruction register first. Then it branches based on conditions like carry flags. Or perhaps the sequencer just increments normally most times.
But you see the horizontal format packs many bits wide. This lets parallel actions happen without extra decoding. I found it faster in some old machines yet wasteful on space. You might prefer vertical which compresses fields instead. It trades speed for smaller memory use overall.
Also the mapping from opcode to starting address uses a decoder. You fetch that initial word then execute the chain. Maybe conditional branches test status bits on the fly. Or unconditional jumps reset the sequence pointer quick. I always liked how this setup lets designers tweak behaviors post fab.
Now think about emulation where one machine mimics another. You program the control store to match foreign opcodes. It turns hardware into software almost. But timing stays tight if the microcycles match clock rates. Perhaps overflow conditions trigger special error routines stored deep.
And the next address logic combines fields from the current word. You get fields for branch address plus select bits. I saw cases where subroutines nest via a small stack. Or direct jumps avoid it for speed. This keeps things modular when you build complex flows.
You asked once why modify after tapeout. Microprograms allow that without respinning chips. I remember cases fixing rare instruction quirks this way. Or adding new features through updates in firmware. It stretches hardware life in embedded gear too.
Perhaps the fetch execute overlap uses separate microsteps. You pipeline the memory access with arithmetic units. I noticed reduced stalls when conditions allow early decode. But hazards still pop up if dependencies chain wrong.
Also field extraction from instructions happens in the first cycle. You route bits straight to the control logic. Maybe sign extension pads shorter operands automatically. Or zero fill works for unsigned cases instead. This avoids extra hardware clutter in the datapath.
I think the whole thing boils down to trading speed for ease. You gain debuggability at cost of extra memory cycles. Or perhaps some hybrid mixes both styles in parts. It depends on the workload you target mostly.
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